Upcoming
STM32 Peripherals That Bite: DMA, Cache and the Debugger
Three peripheral behaviours that cost a week on my own board, and the one-line checks that would have caught each of them at the bench.
- Duration
- 60 minutes
- Platform
- Zoom
- Host
- Jamaludin
Three failure modes, each of which presents as “the firmware is broken” and none of which is a firmware bug.
Session outline
- DMA and the cache — why a coherency problem looks exactly like a race condition, and how the same code passes on one core family and fails on another
- Peripheral clock gating — the register that reads back its reset value and quietly accepts your writes
- The debugger as a bug source — optimisation and timing that only appear when a breakpoint is set
- The DWT cycle counter — measuring instead of guessing, and the three counters worth knowing
Level
Assumes you have brought up a board before and are comfortable with a reference manual. No framework assumed; the examples use bare HAL and Zephyr where it matters.
Recording and slides are published on this page after the session.