Decoupling Capacitors: Where They Belong and Why It Matters
A capacitor placed near the pin it serves is not the same component as one placed nearby. How return paths, loop area and inrush current decide whether a rail stays quiet.
Every board I have been handed for review has had a decoupling problem, and almost none of them were the classic “not enough capacitors” mistake. There were plenty of capacitors. They were just in the wrong places, doing far less than their capacitance suggests.
The part that is not on the datasheet
A 100 nF ceramic capacitor is specified at a frequency. The one on your board sees something else entirely, because three parasitic elements dominate long before the part’s self-resonance becomes interesting:
- ESR — turns the capacitor into a resistor at the frequencies where its inductance matters
- ESL — roughly 1 nH per millimetre of lead, which is the dominant term for a small SMD part
- Mounting — a 0402 on the far side of a board is a different component to the same 0402 next to the pin
The practical consequence: the useful bandwidth of a small ceramic is a few tens of MHz, and beyond that it is an inductor. This is why the bill of materials saying “10 × 100 nF” tells you almost nothing about whether a rail will be quiet.
The loop that actually matters
Decoupling works by providing a local current loop. When an IC pin switches, it draws current instantaneously; the supply network cannot deliver that fast from a distant bulk capacitor. The local capacitor supplies it, and the current returns through the ground plane directly underneath.
The area of that loop sets its inductance, and inductance sets the voltage spike:
V = L · (di/dt)
Three things follow, and they are the entire checklist:
- Place the capacitor on the same layer as the pin. Every via adds inductance to the loop.
- Put the via immediately adjacent to the capacitor’s ground pad. Not at the end of a ground pour.
- Keep the loop footprint small. A tight, direct path from pin to cap to plane beats a short distance with a long return.
A number worth arguing about
A common rule of thumb is that the loop should be under a quarter wavelength of the highest harmonic you care about. That is a reasonable sanity check, not a design rule — it tells you the geometry is not absurd, nothing more. Real designs get validated with the PDN impedance target, not a length.
Bulk capacitance is not a substitute
Bulk and decoupling solve different problems, and mixing them up is expensive:
| Problem | Decoupling | Bulk |
|---|---|---|
| Fast transient current | Yes | No |
| Long-term supply drift | No | Yes |
| Frequency of interest | MHz and up | kHz and down |
| Placement sensitivity | Extreme | Low |
If a rail is drooping at 100 Hz, adding more 100 nF parts will not help. If a rail rings at 40 MHz, a bulk capacitor on the other side of the board contributes nothing at all.
Checking the work
Three checks, in increasing order of effort:
- Read the pin-by-pin decoupling table in the datasheet. Manufacturers specify it for a reason, and the value is often not what the reference design’s BOM suggests.
- Look for symmetry. If a power pin has one capacitor and its neighbour has three, ask why.
- Simulate the PDN. Only worth doing when the board is dense or the interface is fast — but then it is the only check that will actually tell you.
A rail that measures fine on the bench can still fail in the field, because the bench setup adds capacitance the finished product does not have.
What I actually do
I budget the decoupling in the schematic, not in the layout. Every power pin gets its own capacitor on the same layer, in the same loop, before I route a single high-speed net. The layout is then a matter of discipline rather than discovery, and the review conversation stops being about whether there are enough parts and starts being about the two pins that still bother me.
That is the whole practice. It is not exotic, but it is skipped constantly, and skipping it is why rails ring.